// $Module: reg_ive_ccl $
// $RegisterBank Version: V 1.0.00 $
// $Author: andy.tsao $
// $Date: Tue, 07 Dec 2021 11:00:20 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  IVE_CCL_REG_CCL_00  0x0
#define  IVE_CCL_REG_CCL_01  0x4
#define  IVE_CCL_REG_CCL_02  0x8
#define  IVE_CCL_REG_CCL_03  0xc
#define  IVE_CCL_REG_CCL_MODE   0x0
#define  IVE_CCL_REG_CCL_MODE_OFFSET 0
#define  IVE_CCL_REG_CCL_MODE_MASK   0x1
#define  IVE_CCL_REG_CCL_MODE_BITS   0x1
#define  IVE_CCL_REG_CCL_SHDW_SEL   0x0
#define  IVE_CCL_REG_CCL_SHDW_SEL_OFFSET 4
#define  IVE_CCL_REG_CCL_SHDW_SEL_MASK   0x10
#define  IVE_CCL_REG_CCL_SHDW_SEL_BITS   0x1
#define  IVE_CCL_REG_CCL_AREA_THR   0x4
#define  IVE_CCL_REG_CCL_AREA_THR_OFFSET 0
#define  IVE_CCL_REG_CCL_AREA_THR_MASK   0xffff
#define  IVE_CCL_REG_CCL_AREA_THR_BITS   0x10
#define  IVE_CCL_REG_CCL_AREA_STEP   0x4
#define  IVE_CCL_REG_CCL_AREA_STEP_OFFSET 16
#define  IVE_CCL_REG_CCL_AREA_STEP_MASK   0xffff0000
#define  IVE_CCL_REG_CCL_AREA_STEP_BITS   0x10
#define  IVE_CCL_REG_FORCE_CLK_ENABLE   0x8
#define  IVE_CCL_REG_FORCE_CLK_ENABLE_OFFSET 0
#define  IVE_CCL_REG_FORCE_CLK_ENABLE_MASK   0x1
#define  IVE_CCL_REG_FORCE_CLK_ENABLE_BITS   0x1
#define  IVE_CCL_REG_CCL_REGION_NUM   0xc
#define  IVE_CCL_REG_CCL_REGION_NUM_OFFSET 0
#define  IVE_CCL_REG_CCL_REGION_NUM_MASK   0xff
#define  IVE_CCL_REG_CCL_REGION_NUM_BITS   0x8
#define  IVE_CCL_REG_CCL_LABEL_STATUS   0xc
#define  IVE_CCL_REG_CCL_LABEL_STATUS_OFFSET 8
#define  IVE_CCL_REG_CCL_LABEL_STATUS_MASK   0xff00
#define  IVE_CCL_REG_CCL_LABEL_STATUS_BITS   0x8
#define  IVE_CCL_REG_CCL_CUR_AREA_THR   0xc
#define  IVE_CCL_REG_CCL_CUR_AREA_THR_OFFSET 16
#define  IVE_CCL_REG_CCL_CUR_AREA_THR_MASK   0xffff0000
#define  IVE_CCL_REG_CCL_CUR_AREA_THR_BITS   0x10
